Hello! Welcome to Jingyu Pan’s homepage. I am a lead software engineer at Cadence, working on using machine learning to advance VLSI design automation. I completed my Ph.D. in Electrical and Computer Engineering at Duke University, advised by Prof. Yiran Chen in the Computational Evolutionary Intelligence Lab. I earned my B.Eng. in Information Engineering at Zhejiang University in 2020.

My research focuses on machine learning applications for electronic design automation (EDA), spanning AutoML, privacy-preserving ML, ML security, and LLM applications for VLSI design optimization. I have published 6 first-author papers in top EDA conferences (DAC, ICCAD, ASP-DAC) and 2 first-author papers in top journals (TCAD, TODAES). My work has contributed to a Best Paper Award and a Best Paper Nomination at ASP-DAC 2023.

News

• 09/2025: I joined Cadence as a lead software engineer.
• 07/2025: I successfully defended my Ph.D. dissertation.
• 06/2025: Our new paper, “CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs”, is accepted by ICCAD 2025.